rev 2026.10
Status
Built by one author and moving quickly. Some of this runs on the bench every day, some of it has been exercised once, and the interfaces are not frozen yet.
1.0
Working, and next
Maturity varies a lot between features. Some of this runs on the bench daily; some of it has been exercised exactly once.
Working
- Function-block model and config codegen — one file to the whole wiring
- Lock-free multicore channels — host and AMP silicon, both measured
- CAN / CAN-FD with DBC, extended ids, routing, E2E and SecOC
- Network management and NM-gated transmission, sleep and wake on hardware
- Secure boot — signed images, key-separated, verified on the board
- Flight recorder — per-core rings, one dump, one corrected timeline
- System composition — several ECUs from one file, cross-node wiring derived and validated at build time
- Ethernet — a DoIP entity and SOME/IP events and RPC, live on silicon
- Diagnostics — a UDS server per node, on host and target, over CAN and DoIP
- Fault memory — DTCs declared in config, reported through ports, persisted with snapshots
- Persistent data — signals declared
persist, restored before the first handler - Multi-bus on target — the gateway's comm thread owns both CAN buses and forwards routes
Next
- The reference system on the bench — the four boards of the system model are built; the CAN-FD bus, boot and persisted-fault runs are next
- Diagnostics, next rungs — response-pending, DID writes that persist, variant-coding parameters
- Receive checks on target — deadlines and E2E / SecOC verification on the comm thread
- Dual-bank boot and readout protection
- Documentation — the user guide and design notes published here