Measured
Three benches on the host, and the things that only silicon will tell you. Your silicon will differ; these are the numbers from this bench.
Host and silicon
Three benches on the host, and the things that only silicon will tell you.
| transport | SRAM | reads | ns / op | torn | note |
|---|---|---|---|---|---|
| saturating writer — the worst case | |||||
| seqlock | 1× | 216 200 | 4 625.35 | 0 | safe, but the reader spins on retries |
| double | 2× | 6 404 140 | 156.15 | 612 686 | writer laps the reader — tears |
| triple | 3× | 6 701 371 | 149.22 | 0 | wait-free and always safe |
| paced writer @ 100 µs — signals at realistic intervals | |||||
| seqlock | 1× | 30 073 529 | 33.25 | 0 | at interval rates all three are tear-free and equally fast — don't triple your SRAM by default |
| double | 2× | 28 127 863 | 35.55 | 0 | |
| triple | 3× | 29 659 307 | 33.72 | 0 | |
| core | role | micro-model | real generated stack |
|---|---|---|---|
| 0 | 8 buses + 50 blocks | 1.89 % | ~3.8 % |
| 1 | 50 blocks | 1.32 % | ~1.5 % |
| 2 | 50 blocks | 1.22 % | ~1.4 % |
| 3 | 50 blocks | 1.23 % | ~1.5 % |
| — | footprint | — | 448 KB binary · ~0.7 MB Pss |
The right-hand column is the same load through the actual generated stack on real SocketCAN interfaces — config and blocks generated, eight bus-bridge threads polling for real. The IO core costs about 2.5× an application core, and the system sits at roughly fifty times headroom. Scheduling is not where the time goes: a handler dispatch is under a nanosecond, so a 32-handler tick is about 22 ns of Loom.
| finding | measurement | consequence |
|---|---|---|
| exclusives don't arbitrate | 162 torn / 200 000 | the exchange-based triple buffer is not safe on this fabric; cross-core signals use plain stores with sequence stamps instead |
| cross-core bulk stream | ~33 MB/s @ 256 B | the M4's uncached store bandwidth is the wall, not the ring |
| two independent clocks | ±608 µs bound | each core stamps its own timer; the dump carries a measured offset so both cores land on one timeline |
| instruction cache off | 18k … 183k iters/ms | the same loop, swinging tenfold between builds: an M7 fetching from 3-wait-state flash makes throughput a link-address lottery — until the I-cache is switched on |
The last two are the reason the project exists in hardware and not only in a simulator. Neither is visible on a host: on Linux the transports all behave, and the numbers in §1.1 would have been the whole story.